ALevel-CS Chapter 05 Processor Fundamentals

5.01 The von Neumann model of a computer system

Von Neumann

The von Neumann model of a computer system

• The model von Neumann described has the following basic features.
• There is a processor - the central processing unit (CPU).
• The processor has direct access to memory.
• The memory contains a ‘stored program’ (which can be replaced by another at any time) and the data required by the program.
• The stored program consists of individual instructions.
• The processor executes instructions sequentially.

5.02 Central processing unit (CPU) architecture

Key Terms

• Internal clock - controls the cycles of activity within the processor
• System clock - controls the cycles of activity outside the processor
• Accumulator - a general-purpose register that stores a value before and after the execution of an instruction by the ALU

CPU 架构

通俗理解： 计算单元主要执行算术运算、移位等操作以及地址运算和转换；存储单元主要用于保存运算中产生的数据以及指令等；控制单元则对指令译码，并且发出为完成每条指令所要执行的各个操作的控制信号。

• Control Unit(CU):控制单元，协调管理；
• Arithmetic Logic Unit(ALU):数学逻辑单元，接受控制单元CU的命令，负责进行加减乘、与或非运算。
• Register:ALU是负责计算逻辑，具体计算的数据是存放在寄存器（Register，几KB大小）中，寄存器以极高的速度（<1纳秒）与CU和ALU交互。寄存器中的数据是临时寄存的，这些数据和指令会被ALU和CU拿来立即进行计算，如果寄存器中没有CPU想要的数据，CPU会去内存或硬盘中读取。
• BUS:总线，如果寄存器中没有CPU需要的数据，CPU会去内存或硬盘中读取，这个读取内存或其他设备数据的过程，是通过Bus(总线)来实现，计算机中有多条总线。

CPU 指令流程

步骤：

1. Fetch - CPU通过地址总线获取必要的指令并将他们存储到内部存储位置(IAS中)
2. Decode - CPU通过对指令解码理解刚刚获取的指令
3. Execute - CPU执行指令
4. Store - 将执行的结果在存储到内部存储IAS中去

CPU的具体过程：

1. 控制单元CU先取指令(Fetch)；
2. 指令译码(Decode)解析出要执行什么指令；
3. 确认指令是对哪些数据(操作数Operand)进行操作；
4. 将操作数从主存加载到寄存器中；
5. ALU执行指令(Execute)；
6. 结果写回Store；

Register寄存器

MDR(Memory Data Register)

MDR 数据缓冲寄存器，其主要功能是作为CPU和主存、外设之间信息传输的中转站，用以弥补CPU和主存、外设之间操作速度上的差异。

数据寄存器用来暂时存放由主存储器读出的一条指令或一个数据字；反之，当向主存存入一条指令或一个数据字时，也将它们暂时存放在数据寄存器中。

CIR（Current Instruction Register）

CIR 指令寄存器， 用来保存当前正在执行的一条指令。

当执行一条指令时，首先把该指令从主存读取到MDR中，然后再传送至CIR。

PC (Program Counter)

PC 程序计数器，用来指出下一条指令在主存储器中的地址。

在程序执行之前，首先必须将程序的首地址，即程序第一条指令所在主存单元的地址送入PC，因此PC的内容即是从主存提取的第一条指令的地址。

当执行指令时，CPU能自动递增PC的内容，使其始终保存将要执行的下一条指令的主存地址，为取下一条指令做好准备。若为单字长指令，则(PC)+1àPC，若为双字长指令，则(PC)+2àPC，以此类推。

但是，当遇到转移指令时，下一条指令的地址将由转移指令的地址码字段来指定，而不是像通常的那样通过顺序递增PC的内容来取得。

MAR (Memory Address Register)

MAR 地址寄存器，用来保存CPU当前所访问的主存单元的地址。

由于在主存和CPU之间存在操作速度上的差异，所以必须使用MAR来暂时保存主存的地址信息，直到主存的存取操作完成为止。

当CPU和主存进行信息交换，即CPU向主存存入数据/指令或者从主存读出数据/指令时，都要使用MAR和MDR。

ACC (Accumulator)

ACC 累加寄存器，是一个通用寄存器

累加器的功能是：当运算器的算术逻辑单元ALU执行算术或逻辑运算时，为ALU提供一个工作区，可以为ALU暂时保存一个操作数或运算结果。运算器中至少要有一个累加寄存器。

SR (Status Register)

SR 程序状态寄存器，用来表征当前运算的状态及程序的工作方式。

程序状态字寄存器用来保存由算术/逻辑指令运行或测试的结果所建立起来的各种条件码内容，如运算结果进/借位标志（C）、运算结果溢出标志（O）、运算结果为零标志（Z）、运算结果为负标志（N）、运算结果符号标志（S）等，这些标志位通常用1位触发器来保存。

除此之外，程序状态字寄存器还用来保存中断和系统工作状态等信息，以便CPU和系统及时了解机器运行状态和程序运行状态。

因此，程序状态字寄存器是一个保存各种状态条件标志的寄存器。

CPU寄存器架构

程序运行流程

存储器的基本组成：

• 存储单元 - 存放一串二进制代码
• 存储字 - 存储单元中二进制代码的组合
• 存储字长- 存储单元中二进制代码的位数每个存储单元赋予一个地址号
• MAR(Memory Address Register) - 存储器地址寄存器，反映存储单元的个数 2**n。内存中用来存放欲访问存储单元地址的寄存器
• MDR(Memory Data Register) - 存储器数据寄存器，反映存储字长 n。主存中用来存放从某单元读出、或写入某存储单元数据的寄存器;

运算器基本组成：

• ACC(Accumulator) - 累加器，运算器中运算前存放操作数、运算后存放运算结果的寄存器;
• MQ(Multiplier-Quotient Register) - 乘商寄存器，乘法运算时存放乘数、除法时存放商的寄存器。
• X - 此字母没有专指的缩写含义，可以用作任一部件名，在此表示操作数寄存器，即运算器中工作寄存器之一，用来存放操作数;

控制器的基本组成：

PC(Program Counter) - 程序计数器，存放当前欲执行指令的地址，并可自动计数形成下一条指令地址的计数器;
IR(Instruction Register) - 指令寄存器，存放当前正在执行的指令的寄存器;
CU(Control Unit) - 控制单元(部件)，控制器中产生微操作命令序列的部件，为控制器的核心部件;

程序首地址PC：

取指令：PC->MAR->存储体M-MDR->IR

分析指令：IR->CU

执行指令：IR->MAR->M->MDR->ACC

CPU architecture

The active components of the CPU

The two components of the CPU that have an active role in its operation are the arithmetic and logic unit (ALU) (or Arithmetic Logic Unit) and the control unit.

ALU is responsible for the arithmetic or logic processing requirements of the instructions in a running program.

The functions of the control unit are more diverse. One aspect is controlling the flow of data throughout the processor and the rest of the whole computer system. Another is ensuring that program instructions are handled correctly.

Strictly speaking there are two clocks. The first is an internal clock that controls the cycles of activity within the processor. The other is the system clock that controls activities outside the processor.

The CPU will have a defined frequency for its clock cycle, which is usually referred to as the clock speed. The frequency defines the minimum period of time that separates successive activities within the system.

Registers

Registers are storage components which placed very close to the ALU, allow very short access time.

A register is either general purpose or special purpose.

5.03 The system bus

Key Terms

• Address bus - a component that carries an address. This can be to the memory controller to identify a location in memory which is to be read from or written to or it can be to the I/O system to identify the source or destination of the data
• Data bus - a component that can carry data from the processor to the memory or to an output device or can carry data from the memory or from an input device
• Word - a small number of bytes that can be handled as a unit by the computer system

系统总线

数据总线

1. 是CPU与内存或其他器件之间的数据传送的通道。
2. 数据总线的宽度决定了CPU和外界的数据传送速度。
3. 每条传输线一次只能传输1位二进制数据。eg: 8根数据线一次可传送一个8位二进制数据(即一个字节)。
4. 数据总线是数据线数量之和。
5. 和CPU之间双向传输

地址总线

1. CPU是通过地址总线来指定存储单元
2. 地址总线决定了cpu所能访问的最大内存空间的大小。eg: 10根地址线能访问的最大的内存为1024位二进制数据(1B)
3. 地址总线是地址线数量之和。
4. 和CPU之间单向传输

控制总线

1. CPU通过控制总线对外部器件进行控制。
2. 控制总线的宽度决定了CPU对外部器件的控制能力。
3. 控制总线是控制线数量之和。
4. 和CPU之间双向传输

The system bus

A bus is a parallel transmission component with each separate wire carrying a single bit. A bus is a mechanism for data to be transferred from one system component to another.

The system bus connects the CPU to the memory and to the I/O system.

The address bus is connected to the MAR; the data bus to the MDR; and the control bus to the control unit.

The address bus

The sole function of the address bus is to carry an address.

The address bus is a ‘one-way street’.

The data bus

The function of the data bus is to carry data. This might be an instruction, an address or a value.

The data bus is two-way (bidirectional)

The control bus

The control bus is another bidirectional bus which transmits a signal from the control unit to any other system component or transmits a signal to the control unit.

A major use of the control bus is to carry timing signals.

The system clock in the control unit defines the clock cycle for the computer system. The control bus carries timing signals at time intervals dictated by the clock cycle. This ensures that the time that one component transmits data is synchronised with the time that another component reads it.

5.04 Factors contributing to system performance

The processor clock speed could is a very important factor governing the processing speed of the system. This is because one clock cycle defines the shortest possible time that any action can take.

Factors:

• Processor clock speed - One clock cycle defines the shortest possible time that any action can take.
• Cores - Performance improves with increasing number of cores.
• Cache memory - Cache memory is the fastest component of the IAS. Performance improves with increased storage size for the cache and with increased rate of access.
• Address bus width - Special techniques are used when the storage capacity of the memory is too large for direct addressing. Their use affects system performance.

5.05 I/O ports

I/O sports

Each I/O device is connected to an interface called a port. Each port is connected to the I/O or device controller.

Internal port described the connected I/O device is an integral part of the computer system. An external port allows the computer user to connect a peripheral I/O device.

The Universal Serial Bus (USB)

The aim of the plug-and-play concept was to remove the need for technical knowledge so that any computer user could connect a peripheral and start using it straight away.

Specialised multimedia ports

VGA port provides high-resolution screen display which is suitable for most display requirements. The VGA port is not suitable because it does not transmit the audio component.

High Definition Multimedia Interface (HDMI) port will provide a connection to a screen and allow the transmission of high-quality video including the audio component.

5.06 The fetch–execute (F–E) cycle

Fetch -> Decode -> Execute

• This address in the program counter is transferred within the CPU to the MAR.
• During the next clock cycle two things happen simultaneously:
  • the instruction held in the address pointed to by the MAR is fetched into the MDR
  • the address stored in the program counter is incremented.
• The instruction stored in the MDR is transferred within the CPU to the CIR. There are two points to note here.
  • The clock cycle is the one controlled by the system clock which will have settings that allow one data transfer from memory to take place in the time defined for one cycle.
  • In the final step the program counter is incremented by 1. However, the instruction just loaded might be a jump instruction. In this case, the program counter contents will have to be updated in accordance with the jump condition. This can only happen after the instruction has been decoded.

5.07 Register transfer notation

a representation of the fetch stage of the fetch–execute cycle

MAR <- [PC]
PC <- [PC] + 1; MDR <- [[MAR]]
CIR <- [MDR]

5.08 Interrupt handling

CPU中断处理

当CPU（中央处理器）执行一条现行指令的时候，如果外设向CPU发出中断请求，那么CPU在满足响应的情况下，将发出中断响应信号，与此同时关闭中断，表示CPU不在受理另外一个设备的中断。这时，CPU将寻找中断请求源是哪一个设备，并保存CPU自己的程序计数器（PC）的内容。然后，他将转移到处理该中断源的中断服务程序。CPU在保存现场信息，设备服务（如交换数据）以后，将恢复现场信息。在这些动作完成以后，开放中断，并返回到原来被中断的主程序的下一条指令。

中断处理过程：

1. 关中断。CPU关闭中断，即不再接受其他外部中断请求。
2. 保存断点。将发生中断处的指令地址压入堆栈，以使中断处理完后能正确的返回（注意，有可能保存中断处的指令地址，也有可能是中断处的指令的下一条指令的地址，具体情况视中断的类型）。
3. 识别中断源。CPU识别中断的来源，确定中断类型号，从而找到相应的中断处理程序的入口地址
4. （以上三步一般由处理中断的硬件电路完成）保存现场。将发生中断处的有关寄存器（中断服务程序要使用的寄存器）以及标志寄存器的内容压入堆栈。
5. 执行中断服务程序。转到中断服务程序入口开始执行，可在适时时刻重新开放中断，以便允许响应较高优先级的外部中断。
6. （后三步一般软件，即中断处理程序完成）恢复现场并返回。把“保护现场”时压入堆栈的信息弹回寄存器，然后执行中断返回指令，从而返回主程序继续运行。（IRET指令，无操作数，从栈顶弹出3个字，分别送入IP、CS和FLAGS寄存器）

Interrupt handling

• a fatal error in a program
• a hardware fault
• a need for I/O processing to begin
• user interaction
• a timer signal.

Each different interrupt needs to be handled appropriately. Different interrupts might have different priorities.

the existence of an interrupt is only detected at the end of a fetch–execute cycle. This allows the current program to be interrupted and left in a defined state which can be returned to later.

• The contents of the program counter and any other registers are stored somewhere safe in memory.
• The appropriate interrupt handler or Interrupt Service Routine (ISR) program is initiated by loading its start address into the program counter.
• When the ISR program has been executed there is an immediate check to see if further interrupts need handling.
• Further interrupts are dealt with by repeated execution of the ISR program.
• If there are no further interrupts, the safely stored contents of the registers are restored to the CPU and the originally running program is resumed.

辅助阅读

你管这破玩意叫 CPU ？(知乎)

CPU空闲时在干嘛？

漫谈计算机之中断的处理过程